Motion Detection System Based On Background Reconstruction

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Zhang Haoqing,Wang Caicai,Zhou Weikang

Nantong University



This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system.On this basis, Verilog HDL was used to design the AXI4-Stream interface based IP core for image processing, so as to build a high real-time moving target detection system.In our design, we focus on the optimization of processing pipeline, improve the traditional frame difference method, and achieve the optimization goal of saving logical resources through the accumulation compression and reconstruction expansion of cached background frames.


In the detection method, the inter-frame difference method is adopted, which has the characteristics of simple operation, low resource consumption and easy real-time detection.Throughout the design, we need to cache the previous frame as the background frame in order to subtract the absolute value from the latter frame.Combined with the parallel flow characteristics of FPGA itself, this design improves the traditional inter-frame difference method. The previous frame is compressed from the complete grayscale image of 640 * 480 * 8bit through the cumulative compression of 2 * 2 Windows to 320 * 240 * 10bit grayscale image as the compressed background frame. Subsequently, reconstruction and expansion are used for the difference between the compressed frame and the current frame to save BRAM for the cached frame image.The motion track obtained by frame difference is combined with the complete current frame image to obtain the red track, which is captured by surrounding box of blue rectangle.By analogy with this method, 4 x 4 or larger matrix cumulative compression can be used. While a small amount of precision reduction does not have a great impact on detection, BRAM of cached images can be greatly reduced, thus consuming less resources to realize motion detection, effectively reducing costs and adapting to resource-constrained application scenarios.


The whole system, starting from collecting OV7725 camera data, converts Video In AXI4-Stream into stream data.After image processing based on AXI-Stream interface IP core, is made up of the assembly line processing grayscale, median filtering, accumulative compression, cache background frame, frame difference, threshold, reconstruction, expansion and overlapping bounding box to capture and output to the DMA write channels, the DMA write channel image data handling cache to DDR, three caching mechanism was achieved by interrupt.At the same time,DMA read channel always reads the previous frame of the frame being written by the write channel in the three caches, and then converts the AXI4-Stream to Video Out into the line field Video signal output to HDMI driver IP, and finally presents the image processing effect on the external display.



The innovation point of this work is:

1.When the background frame is cached, cumulative compression of 2 x 2 Windows is used, and then reconstruction and expansion are carried out by timing control when calculating with the current frame, which greatly saves BRAM required by the cached frame.

2.Compatible with zynq framework, DDR3 can be used to cache image frames by DMA.

3.Develop AXI4-Stream-based IP with versatility and portability.

4.High real-time performance and stability can be achieved by using the parallel flow of FPGA for efficient image transmission and processing.


System Architecture














Design Demonstration





procedure 2.0






Source Code Github Link

2019年3月12日 09:50